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ICECAL delay line configuration register values

 

phase TH phase ADC icecal*.delayLineCh* fe*.channel*
0 1 0x0908 0x0E01
1 2 0x4910 0x0E01
2 3 0x8918 0x0E01
3 4 0xC920 0x0E01
4 5 0x0929 0x0E01
5 6 0x4931 0x0E01
6 7 0x8939 0x0E01
7 8 0xC941 0x0E01
8 9 0x094A 0x0E01
9 10 0x4952 0x0E01
10 11 0x895A 0x0E01
11 12 0xC962 0x0E01
12 13 0x096B 0x0E01
13 14 0x4973 0x0E01
14 15 0x897B 0x0E01
15 16 0xC983 0x0E01
16 17 0x098C 0x0E01
17 18 0x4994 0x0E01
18 19 0x899C 0x0E01
19 20 0xC9A4 0x0E01
20 21 0x09AD 0x0E01
21 22 0x49B5 0x0E01
22 23 0x89BD 0x0E01
23 24 0xC9C5 0x0E00
24 0 0x0906 0x0E00

-- EduardoPicatosteOlloqui - 2022-06-28

Topic revision: r3 - 2022-07-25 - EduardoPicatosteOlloqui
 

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